The RHFLVDS218 deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmitter clock frequency of 75 MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel. Using a 75 MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/s).
The RHFLVDS218 deserializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size.
All pins have cold spare buffers. These buffers are high impedance when VCC is tied to 0 V.
- 15 to 75 MHz shift clock support
- 50 % duty cycle on receiver output clock
- -4 V to 5 V common-mode range
- Cold sparing all pins
- Fail-safe function
- Narrow bus reduces cable size and cost
- Up to 1.575 Gbps throughput
- Up to 197 Mbytes/s bandwidth
- 325 mV (typ) LVDS swing
- PLL requires no external components
- Rising edge strobe
- Operational environment: total dose irradiation testing to MIL-STD-883 method 1019
- Total-dose: 300 krad (Si)
- Latchup immune (LET > 120 MeV-cm2/mg)
- Compatible with TIA/EIA-644 LVDS standard
|FLAT48 FP||工业||N/A|| |
|FLAT48 EM||工业||N/A|| |
(**) The Material Declaration forms available on st.com may be generic documents based on the most commonly used package within a package family. For this reason, they may not be 100% accurate for a specific device. Please contact our sales support for information on specific devices.